Integrated semiconductor circuits, particularly systems or arrays having transistors each of which represents a binary digit of information, as in read only memories (ROM), have achieved high device or cell densities.
In, e,g., U.S. Pat. No. 3,914,855, filed May 9, 1974, by G. T. Cheney et al, there is described a read only memory wherein the array has transistors made with a thin gate dielectric exhibiting a low threshold voltage for storing a "1" digit of binary information and transistors made of a thick gate dielectric exhibiting a considerably higher threshold voltage for storing the other digit of binary information. Also described is a read only memory wherein ion impurities are implanted to render selected devices inoperative, as defining a "1" digit of binary information, while the remaining devices are operative devices or transistors defining the other digit of binary information.
In U.S. Pat. No. 4,161,039, filed Feb. 6, 1978, by B. Rossler, there is disclosed a memory array utilizing field effect transistors (FET) where information is stored in floating gates and the channel region is made to a short length by employing double-diffusion processing techniques, as disclosed in more detail in "Electronics" Feb. 15, 1971, at pages 99-104. This memory is not a simple read only memory but one that can be reprogrammed after erasing the stored information with ultraviolet light.
U.S. Pat. No. 4,055,837, filed Oct. 22, 1975, by K. U. Stein et al, discloses a single transistor memory wherein information may be stored for long periods of time in a dual insulating structure which is made of silicon nitride formed on silicon dioxide.
Commonly assigned U.S. Pat. No. 4,104,675, filed June 21, 1977 by D. J. DiMaria et al discloses a non-destructive long-term storage system using a floating gate and a single graded energy band gap structure in which each cell may be driven by a relatively low voltage.
In commonly assigned U.S. patent applications Ser. No. 153,359 filed May 27, 1980 by H. N. Kotecha, now U.S. Pat. No. 4,334,292, and Ser No. 160,530 filed June 18, 1980 by H. N. Kotecha and F. W. Wiedman, now U.S. Pat. No. 4,336,603 there is disclosed an improved system for charging and discharging, or writing and erasing, a conductive plate with a charge injector controlled by low voltages. The conductive plate is a floating gate of a cell or transistor, which may be used in an array for storing for long periods of time, on the order of 10 years or more, binary digits of information representing a "0" or a "1" depending upon whether a charge is stored on the floating gate to alter the threshold voltage of the transistor. When using these cells in a memory array, information may be written into or erased from each of the cells individually or a blanket erase may be employed for the entire or a selected section of the array.